The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 14, 1998
Filed:
Oct. 17, 1996
Manzur Gill, Arcola, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
An EPROM or flash EEPROM, which has an array of single-transistor, stacked-gate, memory cells. Active areas for transistor elements are in columns up and down the array, with columns being isolated by thick field oxide strips (220). Word lines (236) and source lines (212) run across the array. Bit lines (216) run along the active area columns to connect transistor drains (218). Bit lines are perpendicular to word lines. Each stacked gate includes a control gate (232) and a floating gate (230), with the latter having a top portion (230b) and a bottom portion (230a) that are separately deposited and etched. The bottom portion (230a) is etched in strips along the active area columns, and define the gate width of each cell. The top portion (230b) overlaps the bottom portion (230a) to improve capacitance between control gate (232) and floating gate (230).