The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 1998

Filed:

Apr. 03, 1995
Applicant:
Inventors:

Jennefer S Hardin, Orangevale, CA (US);

Robert F Kubick, El Dorado Hills, CA (US);

Brian K Langendorf, El Dorado Hills, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ; G06F / ; G11C / ; G11C / ;
U.S. Cl.
CPC ...
711118 ; 39575006 ; 365227 ;
Abstract

A computer system includes an apparatus for conserving power in a tag static random access memory (SRAM). The computer system includes circuitry for placing the tags of the tag SRAM in a reduced power consumption state. The computer system also includes circuitry to power up the tag SRAM out of the reduced power consumption state while maintaining the integrity of the data stored in the tags. The computer system includes a bus, a processor, a cache memory and a memory controller. The memory controller is comprised of a tag static random access memory (SRAM) which includes sense amplifier circuitry and control logic for activating the tag SRAM in response to an address strobe signal (ADS#) from the processor initiating access to the tag SRAM. The memory controller further includes control logic for keeping the tag SRAM activated during an access cycle and for deactivating the tag SRAM, including the sense amplifier circuitry, upon completion of an access cycle to the tag SRAM, thereby placing the tag SRAM in a reduced power consumption state.


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