The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 1998

Filed:

Oct. 23, 1995
Applicant:
Inventors:

Bruce Ernest Whittaker, Mission Viejo, CA (US);

James Henry Jeppesen, III, Lake Forest, CA (US);

Assignee:

Unisys Corporation, Blue Bell, PA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395430 ; 395429 ; 395481 ; 39518507 ; 395308 ; 36518533 ;
Abstract

A network comprising a central processing module and maintenance subsystem which provides a system for rapid loading of instruction words in a microcode RAM whereby microcode instruction words from the maintenance subsystem are preliminarily loaded into a flash memory in the central processing module. A maintenance controller transfers the microcode instruction words from the flash memory over a transfer bus to a data path array which connects to a processor-instruction memory bus for enabling microcode addresses and data words to be rapidly transferred into a microcode RAM instruction memory. A programmable controller activated by the maintenance controller in the central processing module then regulates the transfer of data to the microcode RAM by providing incrementation of the addresses of the instruction words on an automatic basis and thus relieving the processor of this function. Due to the pre-loading of the microcode instruction words into flash memory of the central processing module, there is provided a rapid loading of the microcode RAM during initialization routines without the need to burden the processor or the maintenance subsystem.


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