The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 31, 1998
Filed:
Aug. 30, 1995
Applicant:
Inventors:
Assignee:
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F / ;
U.S. Cl.
CPC ...
327541 ; 327540 ; 327543 ; 327546 ; 323313 ;
Abstract
The gate of an NMOS transistor receives a reference potential, and the source is connected to an output node. A load element is provided between the drain of this transistor and a power supply. First and second inverter circuits sequentially invert a drain potential of the NMOS transistor and transfer it to the gate of a PMOS transistor. The source of the PMOS transistor is connected to a power supply, and the drain is connected to the output node. When the potential of the output node becomes lower than a reference potential, the PMOS transistor is activated until the outputs from the inverter circuits are inverted, thereby charging the output node with a large current.