The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 31, 1998
Filed:
Mar. 11, 1996
Applicant:
Inventor:
Dan Gavish, Haifa, IL;
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R / ; H01H / ;
U.S. Cl.
CPC ...
327 48 ; 327525 ;
Abstract
A clock frequency limiting circuit is disclosed. The clock frequency limiting circuit allows a semiconductor device to be fabricated, packaged and tested before the maximum clock frequency is set. The maximum clock frequency is set by burning a bank of on-chip fuses. The clock frequency limiting circuit counts clock cycles of an applied clock signal for a predetermined amount of time. A comparator compares the maximum clock frequency in the fuse bank and the counted clock cycles. A violation 'kill' signal is asserted if the counted clock cycles exceeds the set maximum clock frequency.