The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 17, 1998
Filed:
Jun. 03, 1996
Craig A Bellows, San Antonio, TX (US);
Landon B Vines, San Antonio, TX (US);
VLSI Technology, Inc., San Jose, CA (US);
Abstract
A purge process for an LPCVD TEOS silicon dioxide deposition method uses a series of five purge cycles to allow low-defect wafer processing with less frequent chamber removal and cleaning. The purge process begins by loading dummy wafers into the chamber. Chamber pressure is reduced to below 20 mTorr. A maximal nonreactant gas flow for two minutes is used to dislodge and carry away contaminants such as flakes from silicon dioxide previously deposited on the chamber wall. After the first four of five purge cycles, the method returns to the reduction of chamber pressure, e.g., by maintaining the vacuum on while the gas sources are turned off. After the fifth cycle, the chamber is slowly filled with nitrogen until ambient pressure is reached. Then the dummy wafers are removed. The system is then ready for processing product wafers with reduced particle counts. The purge process is benign in that it only uses equipment and procedures of the type used during product wafer processing. Maintenance involving chamber removal and cleaning is required much less often so that manufacturing throughput is enhanced.