The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 1998

Filed:

Sep. 27, 1995
Applicant:
Inventors:

Virinder Grewal, Fishkill, NY (US);

Bernhard Poschenrieder, Poughkeepsie, NY (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438633 ; 437631 ; 437639 ; 437692 ;
Abstract

A method of forming a self-aligned overlapping bitline contact, includes steps of first depositing a sacrificial polysilicon on a spacer dielectric film, and thereafter patterning the polysilicon. The polysilicon film is a sacrificial fill-in for a bitline contact stud. The method further includes depositing a middle-of-line (MOL) oxide on the polysilicon, and planarizing the MOL oxide by chemical-mechanical polishing (CMP). Thereafter, the polysilicon is etched and the spacer dielectric film is etched to form a self-aligned bitline contact.


Find Patent Forward Citations

Grewal, Virinder. (1998). Formation of self-aligned overlapping bitline contacts with sacrificial (U.S. Patent No. 5723381). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5723381

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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