Supplementary implantation method for fabricating twin gate cmos

Abstract

A supplementary implantation method for fabricating a twin gate CMOS. A first conductivity-type well region and a second conductivity-type well region, with an isolating region therebetween, are formed on a semiconductor substrate. A gate oxide layer is formed on the surface of the first and second conductivity-type well regions. Next, a polysilicon layer is formed on the surface of the gate oxide layer and is lightly doped with ions of a first conductivity-type. Ions of a second conductivity-type are then implanted in the polysilicon layer above the first conductivity-type well region and thereby convert the layer into a lightly doped layer of the second conductivity-type, while leaving the polysilicon layer above the second conductivity-type well region still lightly doped with the first conductivity-type ions. A polysilicon gate of the second conductivity-type is formed on the first conductivity-type well region, and a polysilicon gate of the first conductivity-type is formed on the second conductivity-type well region. Ions of the first conductivity-type are next implanted in the second conductivity-type well region, and then ions of the second conductivity-type are implanted in the first conductivity-type well region, in separate operations, so as to increase the electrical conductivity of the respective first and second conductivity-type polysilicon gates, while simultaneously forming source/drain regions of the first conductivity-type on the substrate on opposite sides of the first conductivity-type polysilicon gate to establish a first conductivity-type transistor, and similarly forming source/drain regions of the second conductivity-type on the substrate on opposite sides of the second conductivity-type polysilicon gate, to establish a second conductivity-type transistor.