Esd protection for deep submicron cmos devices with minimum tradeoff for

Abstract

Apparatus and process for making the apparatus for electrostatic discharge (ESD) protection of an electronic device, using a silicon controlled rectifier (SCR) configuration. A spaced apart p-well and n-well are formed in a substrate, and spaced apart p+ and n+ contact regions are formed in each well, with an additional n+ or p+ drain tap contiguous to and lying between the two wells. The wells may be formed by a retrograde process or by a conventional process, with or without an epitaxial layer. A first electrode (ground) is connected to the p+ and n+ contact regions and through a polysilicon region to a gate oxide region in the first well. The polysilicon region has a small, controlled poly length. A second electrode is connected to the p+ and n+ contact regions in the second well and to an electrical circuit to be protected against ESD. The second well may be replaced by a portion of the substrate, of opposite electrical polarity to the first well. The triggering voltage for snapback of the SCR device is tunable over a voltage range as low as 5-11 Volts, and the device dynamical resistance in the on-state is about 8-9 Ohms. The SCR device has reduced tradeoff with latchup behavior of the electronic device to be protected.