Autonomous high speed linear space address mode translation for use with

Abstract

Translating between physical and logical (or virtual) address spaces occurs autonomously using information decoded by an address mode translator from command bits within a host CPU issued command. The translator communicates with a hard disc controller unit local microprocessor or microcontroller and controller unit task registers. A host CPU issued command interrupts the local microprocessor and activates the address mode translator by writing to an appropriate controller unit task register using indirect addressing. The address mode translator preferably provides four algorithms, with algorithm selection occurring autonomously according to the decoded command bits. The algorithms provide physical block address to physical CHS cylinder-head-sector conversion, logical CHS to logical block address conversion, and also provide divide and multiply functions, useful for disc caching. Upon completion of the conversion or other function procedure, the address translator signals that the processed result is ready for reading by the controller unit local microprocessor or microcontroller. The translator may be implemented as a microprogrammed sequencer with an instruction set tailored to perform linear address translations and stored in memory associated with the local microprocessor. Alternatively, the instruction set may be downloaded by the microprocessor from disc drive software. The address translator provides the microprocessor with a translated address in a usable form more rapidly than if the local microprocessor had made the translation.