The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 27, 1998
Filed:
Dec. 27, 1995
Applicant:
Inventor:
Bryon G Conley, Hillsboro, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
326 39 ; 326 41 ; 326 93 ;
Abstract
A programmable logic array architecture having improved clock signal to output timing includes a logical AND plane and a logical OR plane. The logical AND plane generates a plurality of intermediary outputs responsive to the plurality of inputs. The logical OR plane then generates a plurality of outputs responsive to the plurality of intermediary outputs. The logical AND plane includes a plurality of semiconductors interconnected in a Type I dynamic logic configuration, and the logical OR plane includes a second plurality of semiconductors interconnected in a Type II dynamic logic configuration.