High-speed image register for graphics display

Abstract

An image register for a graphics display includes a pair of static random access memory (SRAM) devices for respectively storing image data associated with even numbered and odd numbered pixels, which correspond to even numbered and odd numbered addresses. The register includes a counter presettable to an initial value corresponding to a starting address of the stored image data. When the counter outputs an even address (an even state), the even SRAM is enabled for a write operation if an input layer code has a higher priority than the priority of the layer code for the image data stored in the even SRAM, although the odd SRAM is always enabled for a read operation in the even state. The read and write operations occur simultaneously. During the read operation on the odd SRAM, the layer code portion of the image data retrieved therefrom is latched in an associated buffer, whose output is fed to an associated comparator. When the counter is incremented during the next clock cycle, the counter outputs an odd address (an odd state), wherein the odd SRAM is enabled for a write operation if an input layer code has a higher priority than the priority of the retrieved layer code buffered from the prior cycle, although the even SRAM is always enabled for a read operation in the odd state. Both operations occur simultaneously. In both the even and odd states, if the priority of the input layer code is not higher than the priority of the layer code associated with the current image data, the original image data is retained in the even and odd SEAMs, respectively.