The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 1997

Filed:

Dec. 27, 1994
Applicant:
Inventors:

Michiyasu Komatsu, Yokohama, JP;

Yoshitoshi Sato, Yokohama, JP;

Katsuhiro Shinosawa, Kawasaki, JP;

Mineyuki Yamaga, Yomohama, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; C04B / ; H05B / ;
U.S. Cl.
CPC ...
257705 ; 257703 ; 257712 ; 501 97 ; 219200 ;
Abstract

A high thermal conductive silicon nitride structural member of the present invention contains a rare earth element in the range of 1.0 to 7.5 wt. % calculated as oxide thereof and Li, Na, K, Fe, Ca, Mg, Sr, Ba, Mn and B as impurity cationic elements in a total amount not greater than 0.3 wt. %, and has the thermal conductivity not less than 60 W/(m.K), preferably not less than 80 W/(m.K). Also, a high thermal conductive silicon nitride sintered body consists of silicon nitride particles and a grain boundary phase, a crystal compound phase in the grain boundary phase being not less than 20 vol. %, preferably not less than 50 vol. %, with respect to the entire grain boundary phase, and has the thermal conductivity not less than 60 W/(m.K), preferably not less than 80 W/(m.K). A semiconductor package of the present invention comprising a ceramic substrate on which a semiconductor chip is mounted, lead frames joined to the same surface of the ceramic substrate as on which the semiconductor chip is mounted, and bonding wires for electrically connecting the semiconductor chip and the lead frames, wherein the ceramic substrate is formed of the above high thermal conductive silicon nitride sintered body.


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