The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 1997

Filed:

Mar. 08, 1996
Applicant:
Inventors:

Michael J Colwell, Livermore, CA (US);

Teh-Kuin Lee, San Jose, CA (US);

Assignee:

LSI Logic Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257206 ; 257204 ;
Abstract

A base cell design is disclosed, which base cell design includes ten transistor base cell design that includes (1) a first group of four n-type transistors; (2) a second group of four p-type transistors; and (3) a third group of two n-type transistors. The transistors in the first and second groups have substantially the same gate widths, while the transistors of the third group have a substantially smaller gate width. Further, the transistors of the first and second groups all have gates that are aligned in parallel with a first axis, and the transistors of the third group all have gates that are aligned in parallel with a second axis that is substantially perpendicular to the first axis. The first and second groups of transistors each contain at least one set of two transistors which are connected in series and share a source/drain region.


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