The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 1997

Filed:

Jun. 28, 1995
Applicant:
Inventor:

Gary J Lesmeister, Hayward, CA (US);

Assignee:

Credence Systems Corporation, Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R / ; G06F / ; G06F / ;
U.S. Cl.
CPC ...
371 27 ; 324 731 ; 364579 ; 364580 ; 39518308 ;
Abstract

An integrated circuit (IC) tester includes several processing nodes, each accessing a separate terminal of an IC to be tested. The tester receives as input a description of an integrated circuit test to be conducted. The description indicates actions to be taken at each processing node and a time relative to the start of the test that each action is to be taken. The actions may include transmitting a test signal to the IC or sampling an output signal produced by the IC. Before starting the test, the tester converts the description into a set of algorithms for generating test vectors and stores each algorithm in a separate processing node. The test is organized into a succession of test cycles and during the test, each node executes its stored algorithm, generating a separate test vector at the beginning of each test cycle. The test vector indicates an action to be taken by that node during the following test cycle along with a time during the test cycle that the action is to be taken. Each node includes circuits for executing the action at the time indicated.


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