First read cycle circuit for semiconductor memory

Abstract

A novel circuit for initiating a first read cycle when power is first applied to the memory device is disclosed. The circuit compares the ramping up of the word line voltage signal to a stable reference voltage using a comparator. Once the word line voltage reaches a predetermined level, but before it reaches its maximum value, the comparator trips. The transition of the comparator output is sensed by an address transition detection circuit which subsequently triggers a read cycle of the memory, thus creating a dummy read access without any requirement that the input address actually make a transition. A memory access time later, valid data is available at the output of the memory array. A voltage divider is used to divide the word line voltage to a suitable level for input to the comparator. The stable reference voltage serves as the source of the word line signal, besides being input to the comparator. A voltage multiplier is utilized to generate the word line signal from the voltage reference. Alternatively, the word line voltage may be supplied by an external source such as the supply voltage. Both the voltage multiplier and the voltage divider include programmable trimming transistors which allow tuning of their respective outputs. In addition, enable circuitry is included which disables the first read cycle circuitry in order to reduce power consumption after the first read cycle is initiated.