Method and apparatus for improving system memory cost/performance using

Abstract

A computer system is provided with a system memory unit comprising memory address and control signal generation circuitry, a number of banks of extended data out dynamic random access memory (EDODRAM), and a number of registers. The memory address and control signal generation circuitry generates memory addresses for the banks of EDODRAM, advantageously delivered over two address buses. The most significant bits (MSBs) of the memory addresses are buffered and delivered to the banks of EDODRAM over a first address bus, while the least significant bits (LSBs) of the memory addresses are 'split' off and directly delivered, unbuffered, to the banks of EDODRAM over a second address bus to allow a column address to change at a faster rate by bypassing the buffer. Additionally, the memory address and control signal generation circuitry generates control signals for the banks of EDODRAM and the registers, including a column address strobe (CAS) signal with 'shortened' active periods. The banks of EDODRAM accept, store, and output data, in accordance with memory addresses provided. The registers stage data being streamed out of or into the banks of EDODRAM. As a result of the manner in which the memory addresses and the CAS signals are provided, the cycle time of a memory access is reduced, even if slower complementary metal oxide semiconductor (CMOS) technology based circuit elements are used to constitute the memory address and control signal generation circuitry, the EDODRAM, and the registers.