The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 1997

Filed:

Aug. 21, 1996
Applicant:
Inventor:

Noriyuki Ohta, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C / ; H01L / ;
U.S. Cl.
CPC ...
36518501 ; 257316 ;
Abstract

A non-volatile semiconductor memory is composed of split gate type memory cell transistors, each of which comprises a source region and a drain region formed at a principal surface of a semiconductor substrate, separately from each other to form a channel region between the source region and the drain region. This channel region is divided into a first channel region adjacent to the drain region and a second channel region adjacent to the source region. A first gate insulator film is formed on a surface of the first channel region, and a control gate electrode is formed on the first gate insulator film. An insulator layer is formed on the source region and the drain region, and a second gate insulator film is formed on an upper surface and a pair of opposite side surfaces of the control gate electrode and on a surface of the second channel region. A floating gate electrode is formed on the second gate insulator film to have opposite ends terminating on the insulator layer formed on the source region and the insulator layer formed on the drain region, respectively.


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