The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 1997

Filed:

Oct. 30, 1996
Applicant:
Inventor:

Hitoshi Abiko, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 57 ; 437 34 ; 437200 ;
Abstract

A semiconductor device having a CMOS structure having a low resistivity silicide layer in a source/drain region is fabricated. To realize silicide formation for resistivity reduction of the n-type source/drain region, an impurity-free silicon layer is formed thereon before forming a high melting point metal silicide layer. For the n-type source/drain region, ion implantation is made through the silicon layer. It is thus possible to obtain a shallow junction of the p-type source/drain region, prevent ion implantation time increase and obtain quick fabrication without reducing the ion implantation energy.


Find Patent Forward Citations

Abiko, Hitoshi. (1997). Method for fabricating semiconductor device having cmos structure (U.S. Patent No. 5691225). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5691225

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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