The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 1997

Filed:

Dec. 21, 1995
Applicant:
Inventors:

Akishi Nakaso, Oyama, JP;

Koichi Tsuyama, Shimodate, JP;

Kazuhisa Otsuka, Shimodate, JP;

Haruo Ogino, Tochigi-ken, JP;

Yoshihiro Tamura, Shimodate, JP;

Teiichi Inada, Shimodate, JP;

Kazunori Yamamoto, Tsukuba, JP;

Akinari Kida, Tochigi-ken, JP;

Atsushi Takahashi, Yuki, JP;

Yoshiyuki Tsuru, Shimodate, JP;

Shigeharu Arike, Tochigi-ken, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B44C / ; C23F / ;
U.S. Cl.
CPC ...
216 17 ; 216 20 ; 216 36 ;
Abstract

In a process for producing a multilayer printed circuit board comprising drilling holes for via holes in a composite film material containing at least a copper foil and an insulating half-cured adhesive layer, laminating the resulting film material on an innerlayer circuit substrate, ad electrically connecting an innerlayer circuit with an outer layer copper foil, when an adhesive resin flowed into the holes is roughened, or when a composite film material having a copper foil of less than 12 .mu.m thick formed on a carrier is used, or a special cushion material is further laminated on the laminate of the innerlayer circuit substrate and the film material, electrical connection reliability is enhanced and circuit density can be increased with easy steps.


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