Timing signal generator

Abstract

A timing signal generator includes a voltage controlled oscillator (VCO), a logic circuit, N set circuits and N reset circuits and a bistable latch circuit. The VCO produces a set of N reference signals frequency locked to a reference clock signal and distributed in phase so as to evenly resolve the reference clock period into N intervals. The logic circuit asserts ones of N set signals and N reset signals selected by input control words. Each set circuit receives one of the N set signals and one of the N reference signals and briefly couples an output node to high logic level source in response to a leading edge of the received reference signal when its received set signal is asserted. Each reset circuit receives one of the N reset signals and one of the N reference signals and briefly couples the output node to low logic level source in response to a leading edge of its received reference signal when it reset signal is asserted. The bistable circuit maintains the output node at its current logic level after the output node is decoupled from either of the sources. The timing of leading and trailing edges of pulses of the output timing signal may be controlled with a resolution that is 1/Nth of the period of the reference clock by supplying an appropriate control word sequence to the logic circuit.