Selection from a plurality of bus operating speeds for a processor bus

Abstract

A method and apparatus for providing an interface from a processor to a bus. The interface is capable of operating at a speed selected from a plurality of speeds. An execution unit is coupled to a register file. The register file comprises a plurality of registers. Each of the registers of the register file is for storing data. The execution unit is for executing instructions. An instruction cache is coupled to the execution unit. The instruction cache and ROM is for storing instructions that can be used by the execution unit. A reset means is also coupled to the execution unit. Furthermore, a bus speed indication means is coupled to the execution unit and to the register files. The bus speed indication means is for receiving a bus speed indication signal. The bus speed indication signal is for indicating the selected operating speed for the bus interface. The reset signal is provided to the reset means and the bus speed indication signal is provided to the bus speed indication means. Upon receipt of the reset signal, the reset means causes a predetermined string of instructions to be retrieved from the instruction cache and to be executed by the execution unit. A first instruction of the predetermined string of instructions causes a value to be stored in a predetermined register of the register file. The value stored in the predetermined register of the register file is set according to the bus speed indication signal that was provided. A second instruction of the predetermined string of instructions, executed after the first instruction, provides the value stored in the predetermined register of the register file to the bus interface and thereby causes the bus interface to enter a mode wherein the bus interface operates at the selected speed specified by the bus speed indication signal.