The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 11, 1997
Filed:
Jun. 28, 1996
Chau-Neng Wu, Kaohsiung Hsien, TW;
Winbond Electronics Corp., Hsinchu, TW;
Abstract
An electrostatic discharge (ESD) protection circuit connected to an integrated circuit pad for protecting an internal circuit from ESD damage. The ESD protection circuit includes an NMOS/PMOS transistor, a capacitor, and a load. The NMOS/PMOS is configured with a drain connected to the IC pad and a source for connection to the circuit V.sub.SS /V.sub.DD. A gate of the NMOS/PMOS transistor is tied to the source. The capacitor is connected between the IC pad and the bulk of the NMOS/PMOS transistor. The load, which is either another NMOS/PMOS transistor or a resistor, is to be connected between the V.sub.SS /V.sub.DD and the bulk of the NMOS/PMOS transistor. In accordance with the invention, the NMOS/PMOS transistor is fabricated in a P-well/N-well region of a semiconductor substrate. The capacitor includes an IC pad and a polysilicon layer therebelow, with an intervening dielectric layer.