The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 28, 1997
Filed:
Aug. 19, 1996
Douglas W Raymond, Orinda, CA (US);
D Eugene Wedge, Norwell, MA (US);
Philip J Stringer, Otter Shaw, GB;
Teradyne, Inc., Boston, MA (US);
Abstract
A method and apparatus is presented for the automatic generation of boundary scan description language files for integrated circuits incorporating boundary scan circuitry of indeterminate configuration. The user enters basic pin information for the integrated circuit under consideration, along with an identification of which pins are the boundary-scan TAP pins and which are the power and ground pins. The user connects the pins of a sample integrated circuit to the test channels of the apparatus of the invention. The apparatus of the present invention operates in accordance with the method of the present invention automatically to determine: (1) the length of the instruction register; (2) the length of the boundary scan data register; (3) which pins of the integrated circuit are outputs and which pins are inputs, and which are I/O or tri-state outputs; (4) the order that the pins are represented in the boundary scan data register; (5) the identity of the control cells in the boundary scan data register that control I/O and tri-state pins, along with which pins each controls and the sign of the control; (6) the identity of the SAMPLE/PRELOAD instruction; and (7) the identity of the IDCODE instruction and ID code, if present. These parameters are expressed in standard language in a boundary-scan description language file for the integrated circuit under investigation, thus facilitating the use of known automatic program generation software to create test programs.