The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 1997

Filed:

Mar. 24, 1995
Applicant:
Inventors:

Hiroyasu Itou, Nagoya, JP;

Hideya Inagaki, Kasugai, JP;

Assignee:

Nippondenso Co., Ltd., Kariya, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 29 ; 437 34 ; 437 41 ; 437 56 ;
Abstract

An improved manufacturing method for a semiconductor device, which can reduce process inductive fault such as oxidation inductive stacking fault (OSF) and contribute to the improvement of the electric characteristics of the semiconductor device, is disclosed. A thermal oxide film is formed on a semiconductor substrate, then a nitride film is formed and a medium temperature heat treatment is provided to the semiconductor substrate within a temperature range from 600.degree. C. to 1,000.degree. C., whereby an interstitial oxygen concentration can be lowered. Subsequently, ion implantation, etc. are provided as a well region forming process, and a drive-in process is performed by means of a high temperature heat treatment. At this time, ion implantation dose is set to 9.times.10.sup.13 �cm.sup.-2 ! or less, and the temperature of the heat treatment is lowered or the duration of the teat treatment is shortened. After this, an element separation layer process is performed, and a gate oxide film, a gate electrode, a source/drain layer, a CVD oxide film, a contact hole and a metal wire are formed.


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