The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 07, 1997
Filed:
Aug. 22, 1995
William Douglas Cox, San Jose, CA (US);
QuickLogic Corporation, Sunnyvale, CA (US);
Abstract
Node voltages in a net involving non-linear circuit elements are estimated, successively from one point in time to the next, without a computation-intensive step of solving a set of simultaneous equations. An RC tree representing the net is obtained by modeling circuit elements with resistors, capacitors and voltage sources. Voltages on nodes of the RC tree at a second point in time are then estimated given voltages on the nodes at a previous point in time, by: 1) performing a circuit substitution that enforces a backward stepping rule, and 2) performing a DC analysis thereby obtaining node voltages at the second point in time. In this way, estimated node voltages at successive points in time are obtained by repeating the circuit substitution for the next point in time and by repeating the DC analysis to obtain node voltages at the next point in time. The length of time required for the voltage on a selected node to reach a threshold voltage is the estimated propagation delay.