Non-volatile semiconductor memory device with thin insulation layer

Abstract

A non-volatile semiconductor memory device capable of effectively avoiding leak current and whereby avoiding malfunction upon reading out of a data, maintains an erasure gate electrode stacked on a floating gate, at a given potential, such as a grounding potential, when a charge is injected into the floating gate. A thickness of an isolation layer at a portion located beneath the erasure gate electrode and at a side edge portion of a channel to be thinner than the remaining portion. Thus, a current flowing in the vicinity of the interface between the isolation layer and the silicon substrate can be controlled to prevent the leak current from occurring. Therefore, it becomes unnecessary to preliminarily introduce the impurity below the isolation layer to avoid lowering of the withstanding voltage of the PN junction of the N-type diffusion layer of the source and the drain.