The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 1997

Filed:

Jun. 02, 1995
Applicant:
Inventors:

Allan Robert Bertolet, Williston, VT (US);

Kenneth Ferguson, Edinburgh, GB;

Scott Whitney Gould, South Burlington, VT (US);

Eric Ernest Millham, St. George, VT (US);

Ronald Raymond Palmer, Westford, VT (US);

Brian Worth, Milton, VT (US);

Terrance John Zittritsch, Williston, VT (US);

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ; G06F / ;
U.S. Cl.
CPC ...
395800 ; 395311 ; 395297 ; 395309 ; 326 56 ; 364489 ;
Abstract

A programmable array having programmable logic cells, a programmable interconnect network and a programmable I/O system. Two I/O interfaces are provided for respective logic cells about the perimeter of the array. The I/O interfaces comprise input, output and enable paths. Each of these paths has an associated multiplexer. An I/O routing network is positioned about the perimeter of the array. Conductors connecting the I/O interface multiplexers to the programmable interconnect network also intersect, and can be programmably connected to, buses of the I/O routing network.


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