Electrostatic discharge protection circuit triggered by well-coupling

Abstract

An electrostatic discharge (ESD) protection circuit is disposed between a metal pad and a circuit ground, wherein the pad may be an input pad or an output pad. The circuit includes a thick oxide device, a capacitor, and an NMOS transistor. The thick oxide device is configured with its drain and source connected to the pad and circuit ground, respectively. The gate of the thick oxide device is tied to the pad, and the oxide device bulk is connected to the drain of the NMOS transistor. The NMOS transistor is configured with its source connected to the circuit ground and its gate controlled by a power rail. The capacitor is connected between the pad and the bulk of the thick oxide device. The bulk of the device is constructed by a P-well region formed in a substrate. The capacitor is formed between the pad and a polysilicon layer just therebelow, without consuming extra layout area. When a positive-to-ground ESD pulse is conducted to the pad, the capacitor couples the ESD voltage to the well region and turns on the thick oxide device to bypass the ESD stress. Moreover, a diode is connected between the pad and circuit ground by its cathode and anode, respectively, to bypass a negative-to-ground ESD pulse. The diode can be an extra component or a built-in PN junction. In normal operation, the NMOS transistor is powered on and connects the bulk of the device to the circuit ground without floating of the P-well region.