Clock recovery circuit with matched oscillators

Abstract

A clock recovery circuit comprises first and second voltage-controlled oscillators having identical characteristics. The first oscillator is incorporated into a frequency synthesis loop in such a way as to oscillate, in response to a first control voltage, at a frequency equal to a reference frequency multiplied by a number N. The second voltage-controlled oscillator is incorporated into a phase tracking loop which, when activated, locks its oscillation phase relative to that of the received data signal. The second oscillator delivers the recovered clock signal. A comparator determines whether the frequency of the second oscillator, divided by N, satisfies the condition of not deviating from the reference frequency by more than a predetermined limit value. The phase tracking loop is activated only when the latter condition is satisfied, and the first control voltage is fed to the control input of the second oscillator when the condition is not satisfied.