Pmos flash memory cell capable of multi-level threshold voltage storage

Abstract

A P-channel flash EEPROM cell has P+ source and P+ drain regions, and a channel extending therebetween, formed in an N-type well. A thin layer of tunnel oxide is provided over the channel. A poly-silicon floating gate and poly-silicon control gate, separated by a dielectric layer, overlie the tunnel oxide. Programming is accomplished via hot electron injection while erasing is realized by electron tunneling. The threshold voltage of the cell may be precisely controlled by the magnitude of voltage coupled to the floating gate during programming. Since the injection of hot electrons into the floating gate is independent of variations in the thickness of the tunnel oxide layer and the coupling ratio between the floating gate and the control gate, programming operations and data retention are not affected by process variations. In addition, PMOS devices conduct a gate current via hot electron injection over a narrow range of gate voltages, thereby allowing for precise control over the gate current and thus over the charging of the floating gate. This control over the gate current, as well as the independence of the cell's threshold voltage of process parameters, advantageously allows the threshold voltage of the cell to be more accurately controlled, thereby resulting in a more reliable cell capable of storing a greater number of bits of data.