Method and apparatus for sequencing buffers for fast transfer of data

Abstract

A buffer circuit for transferring data between a first slower narrower computer bus and a second wider faster computer bus which buffer circuit includes first and second buffers each capable of storing a plurality of bytes of data equivalent to the width of the second bus, a single address register for holding an address which represents data in either of the two buffers, the lowest order bit of the address register indicating to which one of the two buffers data is being written, first and second registers for storing indications of valid data in the first and second buffers, and a control circuit for controlling the filling of the first and the second buffers in accordance with the byte addresses furnished and the flushing of the first and the second buffers whenever a most significant byte of a buffer has valid data, whenever an attempt is made to write to a buffer address containing valid data, and whenever an attempt is made to load data to a buffer address different than an address in the address register so that sequences of bytes of data are typically accumulated in order in one buffer until an amount of data equal to that which may be transferred on the second wider faster bus is accumulated and then that buffer is flushed to the second wider faster bus while the other buffer is loaded with new data, and so that valid data is not overwritten even though non-sequential addresses are loaded.