Methods of fabricating a transistor cell with a high aspect ratio buried

Abstract

A cell transistor for a dynamic random access memory cell (DRAM) is formed on a substrate, including a capped gate line formed on the substrate, spaced apart source/drain regions formed in the substrate disposed on opposite sides of the capped gate line, a capped channel line overlying and separated from the gate line by an intervening dielectric region and contacting a first of the source/drain regions through the intervening dielectric region, and a second dielectric region covering the capped channel line. To form a buried contact, the transistor is etched with an etchant which etches the intervening dielectric region and the second dielectric region at a first rate and gate line and channel line caps covering the gate and channel lines at a second rate, the first rate being greater than the second rate, for an etching time sufficient to expose a second of the source/drain regions while leaving the gate line and the channel line covered. The first etching rate preferably is at least 20 times greater than the second etching rate. Preferably, the gate line cap and the channel line cap each include silicon nitride, the first interlayer dielectric region includes silicon dioxide and one of borophosphosilicate glass or ozone-tetraethylorthosilicate (O.sub.3 -TEOS), the second dielectric region includes ozone-tetraethylorthosilicate (O.sub.3 -TEOS), the third interlayer dielectric region includes silicon dioxide, and the etchant includes C.sub.3 F.sub.8 gas or C.sub.4 F.sub.8 gas, applied at approximately 3 milliTorr to approximately 4 milliTorr.