The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 26, 1997
Filed:
Sep. 25, 1995
Applicant:
Inventors:
Napoleon W Lee, Milpitas, CA (US);
Derek R Curd, San Jose, CA (US);
Sholeh Diba, Los Gatos, CA (US);
Prasad Sastry, Milpitas, CA (US);
Mihai G Statovici, San Jose, CA (US);
Kameswara K Rao, San Jose, CA (US);
Assignee:
Xilinx, Inc., San Jose, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
36518522 ; 36518518 ; 36518501 ; 36518505 ; 36518524 ; 36518526 ; 36518528 ;
Abstract
An integrated programmable logic device (PLD) includes flash EPROM storage transistors. The PLD includes a multiplexor that selectively provides program, erase, or verify voltages to the storage transistors. The program, erase, and verify voltages may be supplied using external power supplies or may be generated internally by on-chip charge-pump generators. A configurable memory on the PLD is used to adjust the output voltages from each of the on-chip charge-pump generators.