The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 19, 1997
Filed:
Feb. 15, 1996
Richard Gordon Charlton, Essex Junction, VT (US);
George Charles Correia, Essex Junction, VT (US);
Mark Andrew Couture, Milton, VT (US);
Gary Ray Hill, Jericho, VT (US);
Kibby Barth Horsford, Charlotte, VT (US);
Anthony Paul Ingraham, Endicott, NY (US);
Michael David Lowell, Endicott, NY (US);
Voya Rista Markovich, Endwell, NY (US);
Gordon Charles Osborne, Jr, Essex Junction, VT (US);
Mark Vincent Pierson, Binghamton, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method and apparatus for testing semi-conductor chips is disclosed. The individual semiconductor chips have I/O contacts. The apparatus is provided with an interposer that has contacts corresponding to the contacts on the semiconductor chip. Both the chip and the interposer contacts can be any known type including metal ball, bumps, or tabs or may be provided with dendritic surfaces. The chip contacts are first brought into relative loose temporary contact with the contacts on the interposer and then a compressive force greater that 5 grams per chip contact is applied to the chip to force the chip contacts into good electrical contact with the interposer contacts. Testing of the chip is then performed. The tests may include heating of the chip as well as the application of signals to the chip contacts. After testing the chip is removed from the substrate.