The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 12, 1997
Filed:
Dec. 12, 1994
Ching-Yuan Lin, Chin-Chu, TW;
Peng Chao-Chi, Chinchu, TW;
Kyan-Lun Chang, Feng Yuan, TW;
Jermmy J Wang, Kao-hsyung, TW;
Industrial Technology Research Institute, Hsin-Chu, TW;
Abstract
A new method for forming an array of high aspect ratio field emitter for flat panel Field Emission Displays (FEDs) was accomplished. The method involves forming on an insulated substrate an array of parallel cathodes and then depositing a dielectric layer and forming a array of parallel gate electrodes essentially orthogonal to the array of cathode electrodes. Opening are then made in the upper gate electrodes and dielectric layer over the lower cathode electrodes. The field emitters with high aspect-ratios are then formed on the cathode by depositing an emitter material, such as molybdenum, in the opening while heating the substrate to high temperatures. The emitter material is removed elsewhere on the substrate by utilizing a release layer and thereby completing the gated field emitter. This high temperature method results in high aspect-ratio gated emitters that allow the inter-electrode dielectric layer to be increased and thereby improving the circuit performance.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile