The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 05, 1997
Filed:
Mar. 08, 1996
Jeffrey L Rabe, Rancho Cordova, CA (US);
Zohar Bogin, Folsom, CA (US);
Ajay V Bhatt, El Dorado Hills, CA (US);
James P Kardach, San Jose, CA (US);
Nilesh V Shah, Folsom, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A computer system having a responsive low-power mode and a full-power mode of operation. The computer system includes a power consumption controller, a processor and a communication device. The power consumption controller generates an interrupt signal in response to a low power event or a fully operational event. The power consumption controller also generates a clock control signal. The clock control signal is deasserted during the full-power mode of operation and alternatively asserted for a first duration and deasserted for a second duration during the low-power mode of operation. In response to an asserted clock control signal, the processor suppresses the internal clock signal to at least one functional block within the processor and in response to a deasserted clock control signal, the processor transmits the internal clock signal to at least one functional block within the processor. By transmitting the internal clock signal to at least one functional block within the processor during the low-power mode of operation, the processor may respond to communication signals from a communication device during the low-power mode of operation.