The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 05, 1997

Filed:

Oct. 27, 1995
Applicant:
Inventor:

Hironobu Nakao, Kyoto, JP;

Assignee:

Rohm Co., Ltd., Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257324 ; 257326 ; 257314 ; 257295 ;
Abstract

The present invention provides a nonvolatile semiconductor memory which has advantages permitting the cell of the memory circuit to integrate, the memory circuit to be easy to manufacture, and the manufacturing expense to be cut down. The nonvolatile memory 21 comprises a P type well for which a N+ type source 4 and a N+ type drain 3 are provided. A surface of a space between the source 4 and the drain 3 comprises a first portion 10a and a second portion 10b. An insulating layer 6 for holding electrons spans the surface of the space. A memory gate electrode 5 is on the insulating layer 6 and spans the first portion 10a. An insulating body 23 is formed on the surface of the insulating layer 6 so that it connects to the memory gate electrode 5 through an insulating layer 8 and spans the second portion 10b.


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Nakao, Hironobu. (1997). Semiconductor device including nonvolatile memories (U.S. Patent No. 5654568). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5654568

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