The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 22, 1997
Filed:
Jun. 28, 1996
Frankie F Roohoarvar, Cupertino, CA (US);
Christophe J Chevallier, Palo Alto, CA (US);
Micron Quantum Devices, Inc., Santa Clara, CA (US);
Abstract
A memory chip and method for operating a memory chip, in which one or more nodes are monitored to identify an illegal condition, and a halt signal is asserted in response to the illegal condition. If an illegal condition is identified during a high voltage mode in which high voltage is applied across transistors of the chip, assertion of the halt signal is delayed until the end of the high voltage mode. In response to the halt signal, the chip halts an operation such as a memory cell erase operation. By avoiding halt signal assertion during a high voltage mode, the invention avoids problems (e.g., due to the snap back bipolar effect) which could otherwise result due to switching of transistors of the chip during the process of halting chip operation in the high voltage mode. Preferably, each memory cell of the chip is a nonvolatile memory cell such as a flash memory cell, and the chip includes simple logic circuitry including a flip-flop for generating the halt signal in response to a first signal which indicates that an illegal condition has occurred and a second signal which indicates that the chip is in a low voltage mode. After being reset, the flip-flop remains in a first state for as long as the first signal indicates no illegal condition, and enters a second state in response to the first signal indicating an illegal condition. The flip-flop remains in the second state until being reset. The logic circuit outputs the halt signal only when the flip-flop is in the second state and the second signal indicates that the chip is in a low voltage mode.