Method and apparatus for verifying asynchronous circuits using static

Abstract

A method and apparatus for verifying an integrated circuit design composed of both synchronous and asynchronous regions. The computer implemented system imports a design combining synchronous and asynchronous regions and utilizes a static timing analyzer to automatically determine the boundaries of the asynchronous regions including input and output probe points at the inputs and outputs of the asynchronous regions. The static timing analyzer also generates a netlist of the asynchronous regions as well as certain information indicative of the signal arrival times of data sensed over the input probe points of the asynchronous regions. A functional simulator then uses test vectors generated for the primary inputs of the integrated circuit design and automatically determines a set of test vectors specifically for the asynchronous portion by monitoring the input probe points. This can be done for each asynchronous region. The functional simulator also automatically determines a set of expected output data from the generated test vectors by monitoring the output probe points. A full timing gate-level simulator then processes only the asynchronous regions using the generated test vectors, the asynchronous netlist, and the generated arrival times as input and generates an output which is verified against the expected output.