The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 22, 1997
Filed:
Oct. 24, 1995
James J Covino, Essex, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Dynamic CMOS circuits are provided with improved noise immunity. These circuits comprise first and second stacked NFET devices connected respectively between ground and a first node. An input node is coupled to the first NFET device closest to ground and a clock node coupled to the second NFET device closest to the first node. A PFET device is connected between the input node and a node formed by the stacked NFET devices. The first NFET device and the PFET device form an inverter for receiving an input signal, the switch point of the inverter being adjustable by adjusting the PFET/NFET ratio of the inverter, thereby increasing the noise immunity of the circuit.