The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 15, 1997

Filed:

Apr. 19, 1995
Applicant:
Inventors:

John H McCoy, San Carlos, CA (US);

Kyochi Suwa, San Mateo, CA (US);

Assignee:

Nikon Corporation, Tokyo, JP;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01B / ;
U.S. Cl.
CPC ...
356399 ; 356401 ; 250548 ;
Abstract

A prealignment and global alignment system in a semiconductor wafer lithography system includes reflected light microscopes which form images of a wafer near a wafer loading position. The reflected light microscopes are mounted on the perimeter of a main projection lens assembly and have large object areas, typically about 5 mm wide so that features of the wafer are in the object areas even when the wafer is loaded with a very coarse alignment of about .+-.2.5 mm. The prealignment system identifies points on the wafer's edge to align the wafer for a first projection. For second and subsequent projections, the alignment system identifies alignment marks on the wafer to globally align the wafer. Magnification of the microscopes may be increased during global alignment to provide greater accuracy and precision. Prealignment and global alignment are performed while the wafer is at or near the loading position, can be performed in parallel with projection of a pattern on a second wafer, and can be performed quickly with only small movements of the wafer.


Find Patent Forward Citations

McCoy, John. (1997). Alignment system with large area search for wafer edge and global marks (U.S. Patent No. 5648854). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5648854

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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