The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 15, 1997

Filed:

Aug. 04, 1995
Applicant:
Inventors:

Satya Chillara, San Jose, CA (US);

Shahram Mostafazadeh, San Jose, CA (US);

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257666 ; 257693 ; 257700 ; 257701 ;
Abstract

An integrated circuit assembly includes a dielectric flex tape substrate defining a predetermined array of electrically conductive traces and an array of solder balls or solder columns electrically connected to the bottom surface of the flex tape substrate and the traces. An integrated circuit die having a series of input/output pads is supported on the substrate. In one embodiment, a plurality of electrically conductive leads are supported by the flex tape substrate in electrical isolation from and over the conductive traces. A first and second series of bonding wires electrically connect certain ones of the input/output terminals on the integrated circuit die to the electrically conductive leads and conductive traces, respectively. In other embodiments, one or more electrically isolated conductive layers are supported by the dielectric flex tape substrate over the traces and electrically conductive leads. The integrated circuit package assembly, in accordance with any of these embodiments, provides a very high density electrical interconnection arrangement for the integrated circuit die while retaining a small package footprint.


Find Patent Forward Citations

Chillara, Satya. (1997). Tape ball lead integrated circuit package (U.S. Patent No. 5648679). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5648679

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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