Method for fabricating a bit line over a capacitor array of memory cells

Abstract

The present invention provides a method of manufacturing a bit line for a three polysilicon layer DRAM. The method begins by providing a drain region between two spaced transfer gates on a substrate, a first silicon oxide insulation layer over the drain, a capacitor having a polysilicon top plate, the polysilicon top plate extending over the drain, and an inter metal dielectric layer over the resultant structure. First, a bit line contact opening is formed in the inter metal dielectric layer stopping at the top plate over the drain. Next, anisotropic polysilicon etch is used to remove the top plate over the drain. Third, dielectric spacers are formed on the sidewalls of the bit line opening. Fourth, the bitline opening lined by the spacers is filled with a metal to contact the bit line. The spacers insulate the plate electrode from the bit line. Also, the spacers allow a smaller bit line to be used thereby making the memory cell smaller.