Self-clocking sense amplifier optimized for input signals close to vdd

Abstract

A self-clocking sense amplifier includes first and second input nodes and first and second output nodes. A first N-Channel transistor has its drain connected to the first output node and its gate connected to the second output node. A second N-Channel transistor has its drain connected to the second output node and its gate connected to the first output node. An N-Channel pulldown transistor has its source connected to a first supply voltage potential, a drain connected to the drain of the first and second N-Channel transistors, and a gate connected to a pulldown node. A first P-Channel transistor has a source connected to the first input node, a drain connected to the first output node, and a gate connected to the second output node. A second P-Channel transistor has a source connected to the second input node, a drain connected to the second output node, and a gate connected to the first output node. A first P-Channel pullup transistor has a source connected to a second supply voltage potential, a drain connected to the first input node, and a gate connected to a pullup node. A second P-Channel pullup transistor has a source connected to the second supply voltage potential, a drain connected to the second input node, and a gate connected to the pullup node. A N-Channel equalizing transistor has a first drain/source terminal connected to the first output node, a second drain/source terminal connected to the second output node, and a gate connected to the pullup node. A first switch is connected between a first input port and the first input node, a second switch is connected between a second input port and the second input node. Switching circuitry maintains a first state wherein the pullup node is held at a logic low state and the pulldown node is held at a logic high state, and is responsive to a initial edge of a clock pulse to place it in a second state wherein the pullup node is held at a logic high state and the pulldown node is held at a logic low state until the voltages at the first and second output nodes reach a set value, and returns to the first state.