The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 08, 1997
Filed:
Jul. 18, 1995
Makiko Nakamura, Tokyo, JP;
Yasuhiro Fukuda, Tokyo, JP;
Yasuyuki Tatara, Tokyo, JP;
Yusuke Harada, Tokyo, JP;
Hiroshi Onoda, Tokyo, JP;
Oki Electric Industry Co., Ltd., Tokyo, JP;
Abstract
A semiconductor having multi-layer metalization which has a metal layer between aluminum alloy and metal nitride layers, that prevents failure of interconnects when electromigration causes a discontinuity in the aluminum alloy layer. In a one embodiment, the metal of the metal layer and the metal of the nitride layer are both the same metal, such as titanium. In a method of manufacturing the semiconductor device, an insulating layer is formed on a surface of a semiconductor substrate, and in vacuum chambers, the alloy layer is formed on the insulating layer, a metal layer is formed on the alloy layer, and a metal nitride layer is formed on the metal layer in an nitrogen atmosphere. Sputtering, such as DC magnetron sputtering, RF-bias sputtering, or thermal evaporation deposition, may be used to apply the respective nitride, metal and alloy layers. If the same metal is used for the metal layer and the nitride layer, the same vacuum chamber may be used to apply both layers, by replacing an inert gas atmosphere used during metal layer deposition by a nitrogen gas atmosphere for use during the nitride layer deposition.