The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 24, 1997
Filed:
Aug. 10, 1995
Pei-Ing Paul Lee, Lagrangeville, NY (US);
Bernd Vollmer, Wappingers Falls, NY (US);
Darryl Restaino, Modena, NY (US);
Bill Klaasen, Underhills, VT (US);
Siemens Components, Inc., Cupertino, CA (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A multilayer interconnect structure for a semiconductor integrated circuit comprising a base layer of titanium, a second layer of titanium nitride, a third layer of an aluminum alloy and a top layer of titanium nitride. All of the layers contained within the multilayer interconnect structure are deposited by in-situ deposition in an ultra-high vacuum deposition system. The different layers deposited in the deposition system are conducted consecutively without a disruption to the vacuum. Although each layer in the multilayer interconnect structure are deposited within the integrated ultra-high vacuum deposition system, with multiple deposition chambers, the deposition of the different layers is conducted at different temperatures. The time to the electromigration failure of the multilayer interconnect structure, caused by the electromigration of the aluminum alloy, is greatly increased by depositing the aluminum alloy layer at a temperature in excess of 300.degree. C. and preferably between 350.degree. C. and 550.degree. C. The titanium layer and the adjacent titanium nitride layer below the aluminum alloy layer provide the interconnect structure with low resistivity and prevent alloy spiking of the base substrate. As a result, a multilayer interconnect structure provided that has improved electromigration reliability and a low resistance, thereby enabling more dense applications within an integrated circuit.