The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 17, 1997
Filed:
Aug. 17, 1994
Kirk I Hays, Hillsboro, OR (US);
Wayne D Smith, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A computer system provides an expanded register set by employing transparent register stacks for each general purpose register. Each general purpose register and its corresponding set of auxiliary registers form a register stack. No register identification bits are required in processor instructions to reference auxiliary registers. A register set select storage area is a programmable register provided for the storage of a value that identifies the currently active register level. The register set select storage area is loaded using two additional processor instructions provided as part of the present invention. A register set switch is used for selecting a data path to the register level specified by the register set select storage area. A PUSHREG instruction is used to push the register stack pointer down one level. A POPREG instruction is used to move the register stack pointer up one register level. In a alternative embodiment of the present invention, the POPREG and PUSHREG instructions include an argument that specifies the single register stack that is manipulated. In another embodiment of the present invention, register stack underflow or overflow conditions are trapped using an interrupt process. Task switching is implemented with the present invention using a plurality of register stacks each associated with a task frame. In another embodiment of the present invention, the semantics of interrupts to the processor are changed to include an automatic PUSHREG and POPREG instruction execution.
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