The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 10, 1997
Filed:
May. 06, 1996
Bobby B Nikjou, Tempe, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A clock generator which utilizes a SDL, power management circuitry, phase drivers and non-overlap logic all integrated on a single chip to output a set of non-overlapped, complementary clock phases for each processor and for on board peripherals. The present invention also has application for use with multiple discrete processors used on an application or system validation board where one or more of the processors may run at different clock speeds from the others or be stopped. The integrated non-overlap logic reduces the clock skewing among various component on the application board, thus, increasing the overall performance of the system. The present invention is specifically directed to clock generation circuitry including a circuit which receives clock phases generated by a SDL, or from a set of frequency dividers and produces non-overlapped clock phases for each on-board processor and for the on-board peripherals.