The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 03, 1997
Filed:
Nov. 18, 1992
Lars A Eerenstein, Eindhoven, NL;
Mathias N Muris, Eindhoven, NL;
U.S. Philips Corporation, New York, NY (US);
Abstract
A method for generating test patterns to detect an electric shortcircuit, a method for testing electric circuitry while using test patterns so generated, and a tester device for testing electric circuitry with such test patterns. If electric circuitry comprises a plurality of separate nets, a short circuit between an arbitrary pair of nets may be detected by driving the first net at logic zero and the second net at logic one. Measuring the two effective net potentials of the pair of nets will then reveal the short in that two equal potentials would occur. In the case of CMOS technology the driving patterns should also comprise the inverse of the combination above, and also for each pair of nets the number of non-identical overall patterns having the particular 1/0 and 0/1 combinations should be guaranteed and adjustable. The total number of patterns should be minimal. In a test pattern matrix, each column is a single overall pattern; each row is the sequence of signals for the net in question. Each pair of nets is then differentially driven at least twice, either in one, or in both polarities. The minimum Hamming distance between the various rows is equal to two. For the number of nets equal to N the minimum number of test patterns P obeys